1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device using ferroelectric capacitors.
2. Description of the Related Art
A memory device that uses a ferroelectric capacitor as a storage medium, (ferroelectric memory), has been developed and actually used (see, for example, JP 2001-250376A). Ferroelectric memory cells may occasionally vary the signal quantity from the initial state due to thermal stresses and so forth. The ferroelectric memory cells may include such cells that deteriorate earlier even if the initial characteristic is excellent, and such cells that deteriorate after a certain time even if the signal quantity characteristic once becomes better due to thermal stresses and so forth. Therefore, a grasp of the behaviors of different ferroelectric memory cells requires a grasp of accurate cell signal quantities. Thus, an execution of a test mode to grasp the characteristics of the ferroelectric memory cells becomes inevitable.
The signal quantities in cells have been measured in the test mode through a method of directly applying a voltage from external to bit lines to charge all bit lines before measuring, and a method of using dummy cells for the reference potential. The method of directly applying a voltage from external to bit lines to charge bit lines has an advantage because there is no restriction on the level of the reference potential. It requires a time for charging a reference bit line to a desired voltage, however, and accordingly it requires a test time longer by that time. Therefore, it is not suitable for mass-storage ferroelectric memories because of the problem on the test time.
The method of using dummy cells for the reference potential is suitable for mass storage ferroelectric memories because the dummy cells are also available in normal operation and no special configuration for test is required. A configuration of a semiconductor memory device using dummy cells of prior art is described herein. The semiconductor memory device using dummy cells of prior art comprises a pair of bit lines connected to ferroelectric memory cells at one end, dummy capacitors connected at one end to the pair of bit lines, and dummy plate lines connected at one end to the dummy capacitor at the other end. The semiconductor memory device using prior art dummy cells boosts the potential on the reference-side dummy plate line, then compares the potentials on the pair of bit lines, and determines the output signal at “High” or “Low”.
In such a semiconductor memory device using prior art dummy cells, a ferroelectric memory cell has a large capacity. Accordingly, a sufficiently large reference potential can not be achieved unless the dummy capacitor also has a large capacity. If there is a large difference between capacities of ferroelectric memory cells in connection with the pair of bit lines, the dummy capacitor is required to have a large capacity to eliminate the imbalance between the capacities.
Therefore, for such the reason, the dummy capacitor has a large capacity, which has the problem of increasing the area occupied by the dummy capacitor. In addition, if the power supply for providing the reference potential has a restriction on the ability to supply the potential, it is difficult to greatly fluctuate the reference potential to be compared with the read potential as a problem.